1. Technical Field
The present invention relates to host bridges in general, and, in particular, to a translation control entry (TCE) cache within a Peripheral Component Interconnect (PCI) host bridge. Still more particularly, the present invention relates to a method and apparatus for invalidating entries within a TCE cache within a PCI host bridge.
2. Description of Related Art
Generally speaking, a Peripheral Component Interconnect (PCI) host bridge provides communications between a processor and an input/output (I/O) subsystem within a data processing system. The PCI host bridge provides data buffering capabilities to allow read and write data to be transferred between the processor and the I/O subsystem. The I/O subsystem can be a group of PCI devices connected to a PCI bus. When a PCI device on the PCI bus originates a read or write command to a system memory via a direct memory access (DMA), the PCI host bridge translates a PCI address of the DMA to a system memory address of the system memory.
Each PCI device on the PCI bus is associated with a corresponding translation control entry (TCE) table resided within the system memory. The TCE tables can be utilized to preform TCE translations from PCI addresses to system memory addresses. In response to a DMA read or write operation, a corresponding TCE table is read by the PCI host bridge to provide a TCE translation.
Typically, a copy of each TCE that the PCI host bridge has fetched from a TCE table is held by the PCI host bridge in a TCE cache. The PCI host bridge may subsequently reuse any of the TCEs in its TCE cache to determine the system memory location to which a DMA read or write operation will be directed.
When a TCE within a TCE table has been modified by a processor, the PCI host bridge has to remove its own copy of the same TCE from its TCE cache. Since the PCI host bridge is not directly connected to the system bus to which the processor is connected, the PCI host bridge is generally unaware of any modification to the TCE table made by the processor. As such, special hardware connected to the system bus is utilized to detect processor Stores to the TCE table. In response to a detection of a processor Store to the TCE table, the special hardware then sends a DKill command to the PCI host bridge to invalidate the copy of the TCE that has been modified by the processor.
If the special hardware sends a DKill command to the PCI host bridge every time when there is a processor Store to the TCE table, excessive traffic can be generated between the special hardware and PCI host bridge. But more importantly, most of the efforts will be wasted because the PCI host bridge's TCE cache probably does not even have copies of most of the TCEs that are modified by the processor. On the other hand, if the special hardware is to make aware of all the copies of the TCEs stored in the TCE cache by having a TCE directory included within the special hardware, the special hardware would become too complex to be efficient. Consequently, it would be desirable to provide an improved apparatus for invalidating TCEs in a TCE cache within a PCI host bridge.